Image thinning algorithms are widely used in image processing to simplify elaboration preserving geometrical features. Standard approaches are based on iterative methods and on distance transforms. Both techniques are well known to be computationally intensive. In this work we propose a parallel, fast and flexible hardware architecture for image thinning to achieve real-time performance. The test case is the 720 × 576 PAL standard video at 25 frame per second (fps). Synthesis was performed for a Stratix II FPGA EP2S30 and for a standard cell 65nm CMOS technology. The former showed a usage of 4%slices and 1% registers, the latter gave an occupation of 5 kgates for the processing core. The execution time for one frame was 0.03 s on the FPGA and 0.009 s on the 65 nm, resulting in a maximum throughput of 33 fps and 111 fps, respectively.
Hardware accelerator for fast image/video thinning
SAPONARA, SERGIOCo-primo
;FANUCCI, LUCA;TERRENI, PIERANGELO
2014-01-01
Abstract
Image thinning algorithms are widely used in image processing to simplify elaboration preserving geometrical features. Standard approaches are based on iterative methods and on distance transforms. Both techniques are well known to be computationally intensive. In this work we propose a parallel, fast and flexible hardware architecture for image thinning to achieve real-time performance. The test case is the 720 × 576 PAL standard video at 25 frame per second (fps). Synthesis was performed for a Stratix II FPGA EP2S30 and for a standard cell 65nm CMOS technology. The former showed a usage of 4%slices and 1% registers, the latter gave an occupation of 5 kgates for the processing core. The execution time for one frame was 0.03 s on the FPGA and 0.009 s on the 65 nm, resulting in a maximum throughput of 33 fps and 111 fps, respectively.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
