This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.
|Autori interni:||SAPONARA, SERGIO|
|Autori:||S. Saponara; T. Bacchillone; E. Petri; L. Fanucci; R. Locatelli; M. Coppola|
|Titolo:||Design of an NoC interface macrocell with hardware support of advanced networking functionalities|
|Anno del prodotto:||2014|
|Digital Object Identifier (DOI):||10.1109/TC.2012.70|
|Appare nelle tipologie:||1.1 Articolo in rivista|