This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-mum CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to,a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3 divided by 6) even when the losses in power-clock generation are considered.
|Autori:||Blotti A; Saletti R|
|Titolo:||Ultralow-power adiabatic circuit semi-custom design|
|Anno del prodotto:||2004|
|Digital Object Identifier (DOI):||10.1109/TVLSI.2004.836320|
|Appare nelle tipologie:||1.1 Articolo in rivista|