The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 x 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.

Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

PENNELLI, GIOVANNI;
2005

Abstract

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 x 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.
Walker, Ac; Fancey, Sj; Desmulliez, Mpy; Forbes, Mg; Casswell, Jj; Buller, Gs; Taghizadeh, Mr; Dines, Jab; Stanley, Cr; Pennelli, Giovanni; Boyd, Ar; Pearson, Jl; Horan, P; Byrne, D; Hegarty, J; Eitel, S; Gauggel, Hp; Gulden, Kh; Gauthier, A; Benabes, P; Gutzwiller, Jl; Goetz, M; Oksman, J.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/99723
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