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Titolo Data di pubblicazione Autore(i) File
Multiple transient faults in logic: An issue for next generation ICs? 1-gen-2005 Rossi, D.; Omana, M.; Toma, F.; Metra, C.
Coding techniques for low switching noise in fault tolerant busses 1-gen-2005 Nieuwland, A. K.; Katoch, A.; Rossi, D.; Metra, C.
New ECC for crosstalk impact minimization 1-gen-2005 Rossi, D.; Nieuwland, A. K.; Katoch, A.; Metra, C.
Low cost scheme for on-line clock skew compensation 1-gen-2005 Omana, M.; Rossi, D.; Metra, C.
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects 1-gen-2006 Omana, M.; Cazeaux, J. M.; Rossi, D.; Metra, C.
Checker no-harm alarm robustness 1-gen-2006 Rossi, D.; Omaña, M.; Metra, C.; Pagni, A.
Analysis of the impact of bus implemented EDCs on on-chip SSN 1-gen-2006 Rossi, D.; Steiner, C.; Metra, C.
Can clock faults be detected through functional test? 1-gen-2006 Metra, C.; Rossi, D.; Omana, M.; Cazeaux, J. M.; Mak, T. M.
Path (min) delay faults and their impact on self-checking circuits' operation 1-gen-2006 Metra, C.; Omana, M.; Rossi, D.; Cazeaux, J. M.; Mak, T. M.
A novel dual-walled CNT bus architecture with reduced cross-coupling features 1-gen-2006 Rossi, D.; Cazeaux, J. M.; Metra, C.; Lombardi, F.
Latch susceptibility to transient faults and new hardening approach 1-gen-2007 Omana, M.; Rossi, D.; Metra, C.
Configurable error control scheme for NoC signal integrity 1-gen-2007 Rossi, D.; Angelini, P.; Metra, C.
Won't on-chip clock calibration guarantee performance boost and product quality? 1-gen-2007 Metra, C.; Rossi, D.; Mak, T. M.
Modeling crosstalk effects in CNT bus architectures 1-gen-2007 Rossi, D.; Cazeaux, J. M.; Metra, C.; Lombardi, F.
Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic 1-gen-2008 Metra, C.; Rossi, D.; Omana, M.; Jas, A.; Galivanche, R.
Power consumption of fault tolerant busses 1-gen-2008 Rossi, D.; Nieuwland, A. K.; Van Dijk, S. V. E. S.; Kleihorst, R. P.; Metra, C.
Resistive Crossbar Switching Networks for inherently fault tolerant nano LUTs 1-gen-2008 Ma, X.; Huang, J.; Chiminazzo, F.; Rossi, D.; Metra, C.; Lombardi, F.
Risks for signal integrity in system in package and possible remedies 1-gen-2008 Rossi, D.; Angelini, P.; Metra, C.; Campardo, G.; Vanalli, G. P.
Simultaneous switching noise: The relation between bus layout and coding 1-gen-2008 Rossi, D.; Nieuwland, A. K.; Metra, C.
Accurate linear model for SET critical charge estimation 1-gen-2009 Rossi, D.; Cazeaux, J. M.; Omana, M.; Metra, C.; Chatterjee, A.
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