PALIY, MAKSYM Statistiche
PALIY, MAKSYM
Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C
2024-01-01 Sbrana, Christian; Catania, Alessandro; Paliy, Maksym; Pascoli, Stefano Di; Strangio, Sebastiano; Macucci, Massimo; Iannaccone, Giuseppe
Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2
2022-01-01 Migliato Marega, G.; Wang, Z.; Paliy, M.; Giusi, G.; Strangio, S.; Castiglione, F.; Callegari, C.; Tripathi, M.; Radenovic, A.; Iannaccone, G.; Kis, A.
Assessment of Two-Dimensional Materials-based technology for Analog Neural Networks
2021-01-01 Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Iannaccone, Giuseppe
Single-poly floating-gate memory cell options for analog neural networks
2021-01-01 Paliy, M.; Rizzo, T.; Ruiu, P.; Strangio, S.; Iannaccone, G.
Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits
2020-01-01 Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Rizzo, Tommaso; Iannaccone, Giuseppe
Analogue two-dimensional semiconductor electronics
2020-01-01 Polyushkin, D. K.; Wachter, S.; Mennel, L.; Paur, M.; Paliy, M.; Iannaccone, G.; Fiori, G.; Neumaier, D.; Canto, B.; Mueller, T.
Design of a 3T current reference for low-voltage, low-power operation
2018-01-01 De Rose, Raffaele; Crupi, Felice; Paliy, Maksym; Lanuzza, Marco; Iannaccone, Giuseppe
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C | 1-gen-2024 | Sbrana, Christian; Catania, Alessandro; Paliy, Maksym; Pascoli, Stefano Di; Strangio, Sebastiano; Macucci, Massimo; Iannaccone, Giuseppe | |
Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2 | 1-gen-2022 | Migliato Marega, G.; Wang, Z.; Paliy, M.; Giusi, G.; Strangio, S.; Castiglione, F.; Callegari, C.; Tripathi, M.; Radenovic, A.; Iannaccone, G.; Kis, A. | |
Assessment of Two-Dimensional Materials-based technology for Analog Neural Networks | 1-gen-2021 | Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Iannaccone, Giuseppe | |
Single-poly floating-gate memory cell options for analog neural networks | 1-gen-2021 | Paliy, M.; Rizzo, T.; Ruiu, P.; Strangio, S.; Iannaccone, G. | |
Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits | 1-gen-2020 | Paliy, Maksym; Strangio, Sebastiano; Ruiu, Piero; Rizzo, Tommaso; Iannaccone, Giuseppe | |
Analogue two-dimensional semiconductor electronics | 1-gen-2020 | Polyushkin, D. K.; Wachter, S.; Mennel, L.; Paur, M.; Paliy, M.; Iannaccone, G.; Fiori, G.; Neumaier, D.; Canto, B.; Mueller, T. | |
Design of a 3T current reference for low-voltage, low-power operation | 1-gen-2018 | De Rose, Raffaele; Crupi, Felice; Paliy, Maksym; Lanuzza, Marco; Iannaccone, Giuseppe |