Bias temperature instability (BTI) is recognised as the primary parametric failure mechanism in nanometre integrated circuits (ICs). Due to the BTI-induced increase in transistor threshold voltage, circuit performance can degrade noticeably over time. If this induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems. In addition, IC susceptibility to soft errors induced by energetic particles is aggravated by BTI ageing, and so resilience of circuits initially robust against these events decreases over time. In order to assess the impact of BTI ageing on IC reliability, it is of utmost importance to evaluate its impact on both IC performance degradation and soft error rate. This chapter describes methodologies to evaluate BTI ageing accurately and presents results on its impact on performance and soft error rate of combinational circuits and storage elements. The presented results can help designers make the right choices when they are called to design ICs featuring high reliability for their whole lifetime.

The effects of ageing on the reliability and performance of integrated circuits

Rossi D.
Primo
2019-01-01

Abstract

Bias temperature instability (BTI) is recognised as the primary parametric failure mechanism in nanometre integrated circuits (ICs). Due to the BTI-induced increase in transistor threshold voltage, circuit performance can degrade noticeably over time. If this induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems. In addition, IC susceptibility to soft errors induced by energetic particles is aggravated by BTI ageing, and so resilience of circuits initially robust against these events decreases over time. In order to assess the impact of BTI ageing on IC reliability, it is of utmost importance to evaluate its impact on both IC performance degradation and soft error rate. This chapter describes methodologies to evaluate BTI ageing accurately and presents results on its impact on performance and soft error rate of combinational circuits and storage elements. The presented results can help designers make the right choices when they are called to design ICs featuring high reliability for their whole lifetime.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/1047451
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