Error correcting strategy for high speed and high density reliable flash memories

This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of the code correction ability and efficiency. Furthermore, we will show that a minimal increase in the redundancy with respect to the standard case allows a further considerable reduction of the impact on memory access time and area overhead due to the error correction circuitry.