Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator

Convolution Neural Networks are a class of deep neural networks commonly used in audio and video elaborations. Their implementation on the edge represents a complex task due to the limited computational power and low power consumption requirement that characterize these applications. In this paper, a fully on-chip Convolutional Neural Network Field Programmable Gate Array-based hardware accelerator is presented. This approach allows to reduce power consumption due to off-chip memory accesses and aims to reduce design time. Advantages and limitations of the proposed architecture are discussed and a trade-off analysis is provided to give intuitions about the feasibility of this method.