A Single Chip Adaptive Filter for Delta-Modulated Signals

In this paper the VLSI design of a single chip programmable transversal filter for Delta-Modulated signals is presented. In particular, it is shown how the relatively complex function of such a filter is realized with sistolic structures of high regularity and with a high degree of parallelism. With reference to the CMOS technology, really used for the chip, a more detailed description of the main blocks is therefore given. Timing performances of the whole chip are analyzed: the lack of broadcasting allows the chip to work at a frequency near the limits of the used devices.