Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures

This paper presents a peripheral to check for integrity against errors affecting memories in RISC-V architectures. A HW-SW Interface for Error Logging and Reporting to improve Reliability, Availability, and Serviceability (RAS) is proposed. It defines the facilities developed to log details on detected errors into a set of registers, which are then provided to the system software. The developed architecture has been first synthesized on TSMC 7nm Standard-Cell technology and then implemented on an FPGA-based test board featuring the RISC-V CV32E40P core. The proposed peripheral provides a significant degree of flexibility and configurability to effectively satisfy the needs of different application scenarios by selectively incorporating or removing specific features.