Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

This work centres on designing and implementing a Low-Density Parity-Check (LDPC) Encoder on a Xilinx Field Programmable Gate Array (FPGA). The encoder will be part of the Digital Video Broadcasting Satellite 2nd generation (DVB-S2) Transmitter Intellectual Property (IP) for a High Data-Rate Downlink Telemetry System in the context of Earth Exploration Satellite Service. The objective is to design an LDPC encoder with three main features. First, the design will prioritize maximizing data processing speed to ensure the efficient transmission and reception of the payload. Second, the encoder will comply with the DVB-S2 Standard for all possible data rates. This will optimize transmission efficiency by adapting to varying channel conditions, utilizing Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM) techniques. Lastly, the input and output interfaces of the LDPC Encoder will be designed for high reconfigurability, allowing easy adaptation to different operational requirements and facilitating seamless integration into diverse systems. AXI Stream Pipelined Architecture: The LDPC Encoder will utilize an AXI Stream Pipelined architecture. This architecture choice will enhance data transfer efficiency between different functional blocks within the FPGA design, minimizing latency and maximizing overall system performance.