NANNIPIERI, PIETRO Statistiche

NANNIPIERI, PIETRO  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE  

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Titolo Data di pubblicazione Autore(i) File
A PUF-Based Secure Boot for RISC-V Architectures 1-gen-2024 DI MATTEO, Stefano; Zulberti, Luca; Cosimo Lapenna, Federico; Nannipieri, Pietro; Crocetti, Luca; Fanucci, Luca; Saponara, Sergio
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative 1-gen-2024 Nannipieri, Pietro; DI MATTEO, Stefano; Crocetti, Luca; Zulberti, Luca; Fanucci, Luca; Saponara, Sergio
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload 1-gen-2024 Nannipieri, P.; Bartolacci, G.; Bertolucci, M.; Fanucci, L.
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry 1-gen-2023 Quintarelli, G; Bertolucci, M; Nannipieri, P
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments 1-gen-2023 Crocetti, Luca; Nannipieri, Pietro; Di Matteo, Stefano; Saponara, Sergio
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip 1-gen-2023 Monopoli, M; Zulberti, L; Todaro, G; Nannipieri, P; Fanucci, L
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications 1-gen-2023 Monopoli, M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Fault Detection Exploiting Artificial Intelligence in Satellite Systems 1-gen-2023 Ferrante, Nicola; Giuffrida, Gianluca; Nannipieri, Pietro; Bechini, Alessio; Fanucci, Luca
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative 1-gen-2023 Nannipieri, Pietro; Crocetti, Luca; Di Matteo, Stefano; Fanucci, Luca; Saponara, Sergio
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites 1-gen-2023 Zulberti, L.; Monopoli, M.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Inference and Evaluation of Deep Convolutional Neural Networks on Microchip's Hardware Accelerator VectorBlox 1-gen-2023 Dada', M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators 1-gen-2023 Crocetti, L; Nannipieri, P; Di Matteo, S; Fanucci, L; Saponara, S
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario 1-gen-2023 Ciardi, Roberto; Vagaggini, Simone; Marino, Antonino; Nannipieri, Pietro; Fanucci, Luca
SpaceWire/SpaceFibre Analyser Real-Time (SpaceART) system extension to the Wizardlink Protocol 1-gen-2023 Davalle, D.; Dinelli, G.; Benelli, G.; Nannipieri, P.; Ciardi, R.; Fanucci, L.
Towards the Extension of FPG-AI Toolflow to RNN Deployment on FPGAs for On-board Satellite Applications 1-gen-2023 Pacini, T.; Rapuano, E.; Tuttobene, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case 1-gen-2022 Zulberti, Luca; DI MATTEO, Stefano; Nannipieri, Pietro; Saponara, Sergio; Fanucci, Luca
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators 1-gen-2022 Zulberti, Luca; Monopoli, Matteo; Nannipieri, Pietro; Fanucci, Luca
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes 1-gen-2022 Nannipieri, P.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S.
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source 1-gen-2022 Crocetti, L.; Di Matteo, S.; Nannipieri, P.; Fanucci, L.; Saponara, S.
Eye Diagram Analyser for Space High-Speed Serial Links: A Tool for Evaluating Signal Integrity in SpaceFibre Links 1-gen-2022 Sterpaio, L. D.; Dinelli, G.; Davalle, D.; Nannipieri, P.; Fanucci, L.