NANNIPIERI, PIETRO Statistiche
NANNIPIERI, PIETRO
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative
2023-01-01 Nannipieri, Pietro; Crocetti, Luca; Di Matteo, Stefano; Fanucci, Luca; Saponara, Sergio
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators
2023-01-01 Crocetti, L; Nannipieri, P; Di Matteo, S; Fanucci, L; Saponara, S
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario
2023-01-01 Ciardi, Roberto; Vagaggini, Simone; Marino, Antonino; Nannipieri, Pietro; Fanucci, Luca
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case
2022-01-01 Zulberti, Luca; DI MATTEO, Stefano; Nannipieri, Pietro; Saponara, Sergio; Fanucci, Luca
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators
2022-01-01 Zulberti, Luca; Monopoli, Matteo; Nannipieri, Pietro; Fanucci, Luca
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes
2022-01-01 Nannipieri, P.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S.
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source
2022-01-01 Crocetti, L.; Di Matteo, S.; Nannipieri, P.; Fanucci, L.; Saponara, S.
Eye Diagram Analyser for Space High-Speed Serial Links: A Tool for Evaluating Signal Integrity in SpaceFibre Links
2022-01-01 Sterpaio, L. D.; Dinelli, G.; Davalle, D.; Nannipieri, P.; Fanucci, L.
ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components
2022-01-01 Nannipieri, Pietro; Giuffrida, Gianluca; Diana, Lorenzo; Panicacci, Silvia; Zulberti, Luca; Fanucci, Luca; Gerardo Munoz Hernandez, Hector; Hubner, Michael
Satellite High-Speed On-Board Data Handling: From a Wizardlink Equivalent Transceiver To a Full SpaceFibre Interface
2022-01-01 Nannipieri, P.; Fanucci, L.; Dinelli, G.; Sterpaio, L. D.; Marino, A.
SpaceFibre Network Discovery and Configuration Protocol Development
2022-01-01 Nannipieri, P.; Benelli, G.; Davalle, D.; Fanucci, L.; Jameux, D.
SpaceWire Codec VIP: An innovative architecture of UVM-based Verification Environment: SpaceWire Test and Verification, Short Paper
2022-01-01 Vagaggini, S.; Trafeli, M.; Ciardi, R.; Davalle, D.; Santos, L.; Nannipieri, P.; Fanucci, L.
SystemVerilog UVM-based Verification Environment for a SpaceFibre Router
2022-01-01 Gigli, L.; Nannipieri, P.; Zulberti, L.; Vagaggini, S.; Fanucci, L.
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative
2022-01-01 Nannipieri, P.; Matteo, S. D.; Baldanzi, L.; Crocetti, L.; Zulberti, L.; Saponara, S.; Fanucci, L.
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms
2021-01-01 Nannipieri, P.; Di Matteo, S.; Zulberti, L.; Albicocchi, F.; Saponara, S.; Fanucci, L.
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture
2021-01-01 Zulberti, Luca; Nannipieri, Pietro; Fanucci, Luca
Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective
2021-01-01 Nannipieri, P.; Dinelli, G.; Sterpaio, L. D.; Marino, A.; Fanucci, L.
Secure elliptic curve crypto-processor for real-time iot applications
2021-01-01 Di Matteo, S.; Baldanzi, L.; Crocetti, L.; Nannipieri, P.; Fanucci, L.; Saponara, S.
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative
2021-01-01 Nannipieri, P.; Bertolucci, M.; Baldanzi, L.; Crocetti, L.; Di Matteo, S.; Falaschi, F.; Fanucci, L.; Saponara, S.
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation
2021-01-01 Dinelli, G.; Nannipieri, P.; Marino, A.; Fanucci, L.; Dello Sterpaio, L.