Design and Experimental Verification of a 6.25 GHz PLL for Harsh Temperature Conditions in 65 nm CMOS Technology

Reliability is an important characteristic of electronic systems, and it could be undermined by several issues. Among these, wide temperature range represents a threat for the correct operation of electronic systems. Indeed, wide temperature ranges can be experienced in various fields, such as the oil and gas industry, the avionics and automotive fields, or space applications. In these cases, temperatures can reach maximum values up to 160 °C and minimum values down to -40 °C. Additionally, in these fields, the ever-improving sensors’ technology is pushing for increasingly higher data-rates to the control units. This implies the use of high-speed point-to-point connections, which usually exploit Phase-Locked Loops (PLL) to synchronize the communication. These PLLs should then be able to operate in harsh environments and in the GHz range. In this paper, we present the design and the experimental verification of a 6.25 GHz PLL for harsh-temperature conditions from -40 °C up to 160 °C prototyped in a standard 65 nm CMOS technology. We describe the transistor-level design, and we discuss the setups for all the performed measures. The proposed PLL shows a limited performance dependence on temperature variations, which can be compensated further thanks to a tunable bandwidth. Moreover, it achieves fast locking with low area, low power, and a Phase Noise below -98 dBc/Hz @ 1 MHz.