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EnglishThe design principles of reduced-instruction-set computer (RISC) architectures as they apply to VLSI implementation for high-level languages (HLLs) are presented. The nature of general-purpose HLL computations is discussed in terms of static and dynamic program measurements, and the HLL features that need efficient support are identified. CISC (complex-instruction-set computer) and RISC approaches to general-purpose HLL computers are outlined, the effects of instruction-set reduction on both code size and execution time are evaluated, and the delayed-jump concept is introduced. The Berkeley RISC architecture is presented as an example.
| Autori interni: | |
| Autori: | LAZZERINI B |
| Titolo: | Effective VLSI processor architectures for HLL computers: the RISC approach |
| Anno del prodotto: | 1989 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
http://hdl.handle.net/11568/13726
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