This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-mum CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.