CINECA IRIS Institutional Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishThis paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-mum CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.
| Autori interni: | |
| Autori: | Baronti F; Lunardini D; Roncella R; Saletti R |
| Titolo: | A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme |
| Anno del prodotto: | 2004 |
| Digital Object Identifier (DOI): | 10.1109/JSSC.2003.821773 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
http://hdl.handle.net/11568/187265
Copyright © 2021