This paper presents the design and the main performance results of a single-ASIC implementation of the recently proposed extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for code division multiple access (CDMA) transmission. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in blind mode, i.e., it only requires knowledge of the timing of the wanted user's signature code, and it is therefore very well-suited for integration into handheld single-user terminal demodulators. The implementation of the interference-mitigating detector is based on a patented optimized architecture which leads, in 0.25-mum CMOS technology, to a roughly 25 Kgate plus 23-Kbit RAM single-chip ASIC supporting chip rates up to 4 Mchip/s with a maximum internal clock frequency of 32.768 MHz, The main design drivers are thoroughly discussed, and the relevant performance results are compared to the theoretical behavior. A possible extension to multirate CDMA systems adopting orthogonal variable spreading factor (OVSF) sequences is also briefly addressed.

VLSI Implementation of a CDMA Blind Adaptive Interference-Mitigating Detector

FANUCCI, LUCA;GIANNETTI, FILIPPO;LUISE, MARCO
2001

Abstract

This paper presents the design and the main performance results of a single-ASIC implementation of the recently proposed extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for code division multiple access (CDMA) transmission. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in blind mode, i.e., it only requires knowledge of the timing of the wanted user's signature code, and it is therefore very well-suited for integration into handheld single-user terminal demodulators. The implementation of the interference-mitigating detector is based on a patented optimized architecture which leads, in 0.25-mum CMOS technology, to a roughly 25 Kgate plus 23-Kbit RAM single-chip ASIC supporting chip rates up to 4 Mchip/s with a maximum internal clock frequency of 32.768 MHz, The main design drivers are thoroughly discussed, and the relevant performance results are compared to the theoretical behavior. A possible extension to multirate CDMA systems adopting orthogonal variable spreading factor (OVSF) sequences is also briefly addressed.
Fanucci, Luca; Letta, E; DE GAUDENZI, R; Giannetti, Filippo; Luise, Marco
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/187348
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