Validation of the DJOSER analytical thermal simulator for electronic power devices and assembling structures

The present communication deals with the tests for the validation of the DJOSER steady-state thermal simulation program, purposely designed for power electronic assembling structures and which is based on the resolution of analytical relationships. The validation experiments were carried out theoretically by comparing the thermal maps with those obtained using standard finite-elements programs and yielding temperature accuracy below 1%. Experimental tests were also performed on purposely built multi-layer structures and industrial circuits with power diodes mounted in naked-chip configuration. The simulated maps were compared with accurate thermo-graphic recordings and showed a good agreement, testifying the validity of the mathematical model.