In this paper, we present a design approach based on a reassessment of design priorities to obtain robust circuits with respect to process variability. We show that if we address variability as one of the main issues in circuit design, and make it inform our very first design choices, we are able to significantly reduce dispersion of circuit characteristics without degrading of the other performance figures. We apply this variability-aware approach to the design of a nanopower reference voltage generator in 0.18-μm CMOS technology. The result is a BJT-based topology, which provides a reference voltage of about 241 mV from a 1 V supply voltage. Measurements on 20 samples from a single batch show that the reference voltage exhibits a relative standard deviation of 0.18%, while consuming only 68.3 nW. This is comparable with the performance of references that are either trimmed or consume much more power. This reduced process sensitivity comes at the cost of a significant increase of die area (0.28 mm2).

Variability-aware design of a bandgap voltage reference with 0.18% standard deviation and 68 nW power consumption

Di Pascoli, S.
Co-primo
;
Iannaccone, G.
Co-primo
2018

Abstract

In this paper, we present a design approach based on a reassessment of design priorities to obtain robust circuits with respect to process variability. We show that if we address variability as one of the main issues in circuit design, and make it inform our very first design choices, we are able to significantly reduce dispersion of circuit characteristics without degrading of the other performance figures. We apply this variability-aware approach to the design of a nanopower reference voltage generator in 0.18-μm CMOS technology. The result is a BJT-based topology, which provides a reference voltage of about 241 mV from a 1 V supply voltage. Measurements on 20 samples from a single batch show that the reference voltage exhibits a relative standard deviation of 0.18%, while consuming only 68.3 nW. This is comparable with the performance of references that are either trimmed or consume much more power. This reduced process sensitivity comes at the cost of a significant increase of die area (0.28 mm2).
Cucchi, F.; Di Pascoli, S.; Iannaccone, G.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/933236
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