MARINO, ANTONINO Statistiche
MARINO, ANTONINO
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE
Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective
2021-01-01 Nannipieri, P.; Dinelli, G.; Sterpaio, L. D.; Marino, A.; Fanucci, L.
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation
2021-01-01 Dinelli, G.; Nannipieri, P.; Marino, A.; Fanucci, L.; Dello Sterpaio, L.
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface
2020-01-01 Nannipieri, Pietro; Dinelli, Gianmarco; Marino, Antonino; Dello Sterpaio, Luca; Leoni, Alessandro; Fanucci, Luca; Davalle, Daniele
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA
2020-01-01 Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Dinelli, G.; Fanucci, L.
CCSDS 131.2-B-1 telemetry transmitter: A VHDL IP core and a validation architecture on board RTG4 FPGA
2020-01-01 Meoni, G.; Cassettari, R.; Bertolucci, M.; Marino, A.; Davalle, D.; Trafeli, M.; Fanucci, L.
Design of a SpaceFibre High-Speed Satellite Interface ASIC
2020-01-01 Nannipieri, P.; Dinelli, G.; Dello Sterpaio, L.; Marino, A.; Fanucci, L.
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus
2020-01-01 Dinelli, G.; Meoni, G.; Nannipieri, P.; Dello Sterpaio, L.; Marino, A.; Fanucci, L.
SpaceART SpaceWire and SpaceFibre Analyser Real-Time
2020-01-01 Marino, A.; Leoni, A.; Sterpaio, L. D.; Nannipieri, P.; Dinelli, G.; Benelli, G.; Davalle, D.; Fanucci, L.
A complete egse solution for the spacewire and spacefibre protocol based on the pxi industry standard
2019-01-01 Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Dinelli, G.; Davalle, D.; Fanucci, L.
A PXI based implementation of a TLK2711 equivalent interface
2019-01-01 Nannipieri, P.; Dello Sterpaio, L.; Marino, A.; Fanucci, L.
Design of a spacewire/spacefibre EGSE system based on PXI industry standard
2019-01-01 DELLO STERPAIO, Luca; Nannipieri, P.; Marino, A.; Fanucci, L.
Exploiting LabVIEW FPGA Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards
2019-01-01 Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Fanucci, L.
Design and implementation of a complete test equipment solution for SpaceWire links
2018-01-01 Marino, Antonino; Sterpaio, Luca Dello; Fanucci, Luca
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective | 1-gen-2021 | Nannipieri, P.; Dinelli, G.; Sterpaio, L. D.; Marino, A.; Fanucci, L. | |
| The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation | 1-gen-2021 | Dinelli, G.; Nannipieri, P.; Marino, A.; Fanucci, L.; Dello Sterpaio, L. | |
| A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface | 1-gen-2020 | Nannipieri, Pietro; Dinelli, Gianmarco; Marino, Antonino; Dello Sterpaio, Luca; Leoni, Alessandro; Fanucci, Luca; Davalle, Daniele | |
| AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA | 1-gen-2020 | Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Dinelli, G.; Fanucci, L. | |
| CCSDS 131.2-B-1 telemetry transmitter: A VHDL IP core and a validation architecture on board RTG4 FPGA | 1-gen-2020 | Meoni, G.; Cassettari, R.; Bertolucci, M.; Marino, A.; Davalle, D.; Trafeli, M.; Fanucci, L. | |
| Design of a SpaceFibre High-Speed Satellite Interface ASIC | 1-gen-2020 | Nannipieri, P.; Dinelli, G.; Dello Sterpaio, L.; Marino, A.; Fanucci, L. | |
| Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus | 1-gen-2020 | Dinelli, G.; Meoni, G.; Nannipieri, P.; Dello Sterpaio, L.; Marino, A.; Fanucci, L. | |
| SpaceART SpaceWire and SpaceFibre Analyser Real-Time | 1-gen-2020 | Marino, A.; Leoni, A.; Sterpaio, L. D.; Nannipieri, P.; Dinelli, G.; Benelli, G.; Davalle, D.; Fanucci, L. | |
| A complete egse solution for the spacewire and spacefibre protocol based on the pxi industry standard | 1-gen-2019 | Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Dinelli, G.; Davalle, D.; Fanucci, L. | |
| A PXI based implementation of a TLK2711 equivalent interface | 1-gen-2019 | Nannipieri, P.; Dello Sterpaio, L.; Marino, A.; Fanucci, L. | |
| Design of a spacewire/spacefibre EGSE system based on PXI industry standard | 1-gen-2019 | DELLO STERPAIO, Luca; Nannipieri, P.; Marino, A.; Fanucci, L. | |
| Exploiting LabVIEW FPGA Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards | 1-gen-2019 | Dello Sterpaio, L.; Marino, A.; Nannipieri, P.; Fanucci, L. | |
| Design and implementation of a complete test equipment solution for SpaceWire links | 1-gen-2018 | Marino, Antonino; Sterpaio, Luca Dello; Fanucci, Luca |