Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus

Nowadays, requirements for satellite electronics are becoming more stringent due to the increasing complexity of space missions. In particular, data rate requirement is growing up due to the adoption of high-speed payloads such as Synthetic Aperture Radars and hyper-spectral imagers that overcome the capability of state-of-the-art on-board data handling system. The European Space Agency answered to this request introducing a new high-speed communication protocol, SpaceFibre. At the same time, data collected by high-speed interfaces may be processed on-board with specific hardware or general-purpose microprocessor such as the LEON3. The aim of this paper is to describe the integration of a SpaceFibre IP core in the Cohbam Gaisler GRLIB library, to integrate the functionalities offered by the SpaceFibre CODEC with the potential of the LEON3 microprocessor. Implementation results on a Xilinx Virtex-6 and an analysis of the performance of the SpaceFibre interface on an AMBA 2.0 AHB bus are presented.