In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16 communication lanes). This work proposes the design of a SpaceFibre interface Application Specific Integrated Circuit. The block diagram of the system is presented, together with results in terms of area occupation and power consumption (excluding serialiser-deserialiser circuitry) after the synthesis on a 65 nm CMOS technology.
Design of a SpaceFibre High-Speed Satellite Interface ASIC
Nannipieri P.;Dinelli G.;Dello Sterpaio L.;Marino A.;Fanucci L.
2020-01-01
Abstract
In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16 communication lanes). This work proposes the design of a SpaceFibre interface Application Specific Integrated Circuit. The block diagram of the system is presented, together with results in terms of area occupation and power consumption (excluding serialiser-deserialiser circuitry) after the synthesis on a 65 nm CMOS technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
