This paper describes the VLSI design of a single-chip FIR filter to be employed as co-processor in a board for acoustic echo cancellation. The filter provides for the emulation of the variable response of the acoustic channel and thus has to be adaptive. Bit-level systolic macrocells are used as building blocks of the circuit, in order to achieve the high performance needed and to satisfy the complexity requirements. The circuit consists of a systolic core where the computation is performed. characterized by a high clock frequency, an easy and regular design, and of a low-speed interface to the rest of the board. Peculiar characteristics are also the high number of taps (1024), the techniques used to reduce the area occupied by the 16 x 16 multiplier, and those used to synchronize the internal clock to the external one. The circuit was designed with a 1.2-mu-m CMOS technology. It employs more than 300 000 transistors and its clock frequency is greater than 70 MHz.
|Autori interni:||RONCELLA, ROBERTO|
|Autori:||Roncella R.; Saletti R.; Terreni P.; Toncelli C.|
|Titolo:||Single-Chip Adaptive FIR Filter for Acoustic Echo Canceler Board|
|Anno del prodotto:||1992|
|Digital Object Identifier (DOI):||10.1016/0165-1684(92)90080-G|
|Appare nelle tipologie:||1.1 Articolo in rivista|