An eight-channel, 1 ns bin-size, 23 b dynamic range, single-chip, multihit, time-to-digital converter (TDC) is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted, The chip can execute common-start or common-stop operations on the trailing, leading, or both transitions of the input channels; it stores at least 32 events/channel with a double-hit resolution of 16 ns, A prototype of about 120 mm(2) has been integrated into a double-metal, single-poly, n-well 1 mu m CMOS process, and its performance has been compared to that of similar devices. Test results show that a differential nonlinearity error of +/-1%, an integral nonlinearity less than 0.2 least significant bit (LSB), and a time resolution of 0.443 LSB-significantly better than those of comparable TDC's and very close to the theoretical limit of 0.408 LSB-have been achieved.