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EnglishAn eight-channel, 1 ns bin-size, 23 b dynamic range, single-chip, multihit, time-to-digital converter (TDC) is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted, The chip can execute common-start or common-stop operations on the trailing, leading, or both transitions of the input channels; it stores at least 32 events/channel with a double-hit resolution of 16 ns, A prototype of about 120 mm(2) has been integrated into a double-metal, single-poly, n-well 1 mu m CMOS process, and its performance has been compared to that of similar devices. Test results show that a differential nonlinearity error of +/-1%, an integral nonlinearity less than 0.2 least significant bit (LSB), and a time resolution of 0.443 LSB-significantly better than those of comparable TDC's and very close to the theoretical limit of 0.408 LSB-have been achieved.
| Autori interni: | |
| Autori: | Andreani P.; Bigongiari F.; Roncella R.; Saletti R.; Terreni P.; Bigongiari A.; Lippi M. |
| Titolo: | Multihit multichannel time-to-digital converter with +/- 1% differential nonlinearity and near optimal time resolution |
| Anno del prodotto: | 1998 |
| Digital Object Identifier (DOI): | 10.1109/4.663573 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
http://hdl.handle.net/11568/204275
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