A novel algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described in this paper. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve a high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by the operation on three interleaved independent sequences for a total of 75 samples, is also presented as a demonstrator. The throughput relevant to one sequence is 1/3 in this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-mum CMOS technology have been successfully tested at a clock frequency over 70 MHz.
70-MHz 2-μm CMOS Bit-level Systolic Arrat Median Filter
RONCELLA, ROBERTO;SALETTI, ROBERTO;TERRENI, PIERANGELO
1993-01-01
Abstract
A novel algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described in this paper. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve a high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by the operation on three interleaved independent sequences for a total of 75 samples, is also presented as a demonstrator. The throughput relevant to one sequence is 1/3 in this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-mum CMOS technology have been successfully tested at a clock frequency over 70 MHz.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
