NANNIPIERI, PIETRO Statistiche
NANNIPIERI, PIETRO
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE
Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform
2025-01-01 Zulberti, L.; Monopoli, M.; Nannipieri, P.; Moranti, S.; Thys, G.; Fanucci, L.
FPG-AI RNN: A Technology-Agnostic Framework for the Automatic Acceleration of LSTM/GRU-Based Models on FPGAs
2025-01-01 Pacini, T.; Nannipieri, P.; Moranti, S.; Fanucci, L.
Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review
2025-01-01 Mystkowska, G.; Monopoli, M.; Nannipieri, P.; Zulberti, L.; Merodio Codinachs, D.; Fanucci, L.
RADSAFiE: A Netlist-Level Fault Injection User Interface Application for FPGA-Based Digital Systems
2025-01-01 Monopoli, M.; Biondi, M.; Nannipieri, P.; Moranti, S.; Fanucci, L.
Toward Reliable Onboard AI in Space: A Fault-Tolerant Soft GPU-Based System-on-Chip
2025-01-01 Monopoli, M.; Biondi, M.; Moranti, S.; Nannipieri, P.; Fanucci, L.
A PUF-Based Secure Boot for RISC-V Architectures
2024-01-01 DI MATTEO, Stefano; Zulberti, Luca; Cosimo Lapenna, Federico; Nannipieri, Pietro; Crocetti, Luca; Fanucci, Luca; Saponara, Sergio
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative
2024-01-01 Nannipieri, Pietro; DI MATTEO, Stefano; Crocetti, Luca; Zulberti, Luca; Fanucci, Luca; Saponara, Sergio
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload
2024-01-01 Nannipieri, P.; Bartolacci, G.; Bertolucci, M.; Fanucci, L.
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
2024-01-01 Mystkowska, G.; Zulberti, L.; Monopoli, M.; Nannipieri, P.; Fanucci, L.
Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems
2024-01-01 Vagaggini, Simone; Davalle, Daniele; Nannipieri, Pietro; Fanucci, Luca
SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems
2024-01-01 Zulberti, L.; Monorchio, A.; Monopoli, M.; Mystkowska, G.; Nannipieri, P.; Fanucci, L.
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry
2023-01-01 Quintarelli, G; Bertolucci, M; Nannipieri, P
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments
2023-01-01 Crocetti, Luca; Nannipieri, Pietro; Di Matteo, Stefano; Saponara, Sergio
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip
2023-01-01 Monopoli, M; Zulberti, L; Todaro, G; Nannipieri, P; Fanucci, L
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications
2023-01-01 Monopoli, M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Fault Detection Exploiting Artificial Intelligence in Satellite Systems
2023-01-01 Ferrante, Nicola; Giuffrida, Gianluca; Nannipieri, Pietro; Bechini, Alessio; Fanucci, Luca
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative
2023-01-01 Nannipieri, Pietro; Crocetti, Luca; Di Matteo, Stefano; Fanucci, Luca; Saponara, Sergio
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites
2023-01-01 Zulberti, L.; Monopoli, M.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Inference and Evaluation of Deep Convolutional Neural Networks on Microchip's Hardware Accelerator VectorBlox
2023-01-01 Dada', M.; Zulberti, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators
2023-01-01 Crocetti, L; Nannipieri, P; Di Matteo, S; Fanucci, L; Saponara, S