A Robust and Portable All-Digital TRNG Circuit for Extending the Instruction Set Architecture of RISC-V Processors

All-digital True Random Number Generators (TRNGs) play a crucial role in enhancing hardware security by providing native entropy sources directly within the processor pipeline. Their integration into open architectures such as RISC-V enables the extension of the Instruction Set Architecture (ISA) with secure, hardware-level random number generation capabilities essential for cryptographic operations. This work presents the design and validation of an all-digital True Random Number Generator (TRNG) for seamless integration with RISC-V processors via a custom interface. The proposed circuit has been developed using SystemVerilog and leverages Fibonacci Galois Ring Oscillators (FiGaROs), which use jitter and metastability as entropy sources to ensure high quality randomness. The TRNG has been integrated with the VECtor processor (VEC) core of the European Processor ACcelerator (EPAC) chip through a custom Control and Status Register (CSR) interface, enabling its use as a secure entropy source within the RISC-V instruction set architecture for cryptographic applications. The validation campaign is based on the typical main statistical suites of reference organizations in the field of security and cryptography and demonstrates that our solution offers both high-security standards and independence from both the implementation technology and the operating frequency chosen for the TRNG circuit, reporting an entropy per bit (in terms of Shannon entropy) of 0.9999 in all test cases, while always passing the pass-fail criteria for randomness. In addition, our circuit offers the highest entropy rate for both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) solutions, as well as an efficiency in terms of entropy rate per resource consumption that is approximately 96 to 257 times that of the other solutions in the case of ASIC implementation.