MESTICE, MARCO Statistiche

MESTICE, MARCO  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE  

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Risultati 1 - 10 di 10 (tempo di esecuzione: 0.031 secondi).
Titolo Data di pubblicazione Autore(i) File
An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments 1-gen-2024 Mestice, Marco; Ciarpi, Gabriele; Rossi, Daniele; Saponara, Sergio
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas 1-gen-2024 Ciarpi, Gabriele; Noccetti, Ettore; Ceragioli, Luca; Mestice, Marco; Rossi, Daniele; Saponara, Sergio
Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications 1-gen-2024 Ciarpi, Gabriele; Mestice, Marco; Rossi, Daniele; Saponara, Sergio
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments 1-gen-2023 Ciarpi, G.; Mestice, M.; Rossi, D.; Palla, F.; Saponara, S.
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications 1-gen-2023 Ciarpi, Gabriele; Mestice, Marco; Rossi, Daniele; Palla, Fabrizio; Saponara, Sergio
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology 1-gen-2023 Ciarpi, G.; Puccioni, G.; Mestice, M.; Monda, D.; Rossi, D.; Saponara, S.
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS technology 1-gen-2023 Mestice, M.; Biondi, G.; Ciarpi, G.; Rossi, D.; Saponara, S.
Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology 1-gen-2023 Ciarpi, Gabriele; Monda, Danilo; Mestice, Marco; Rossi, Daniele; Saponara, Sergio
Analysis and design of integrated blocks for a 6.25 ghz spacefibre pll 1-gen-2020 Mestice, M.; Neri, B.; Ciarpi, G.; Saponara, S.
Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard 1-gen-2019 Mestice, Marco; Neri, Bruno; Saponara, Sergio