This paper presents a System-on-Chip (SoC) implementation of a cryptographic hardware accelerator supporting multiple AES based block cypher modes, including the more advanced CMAC, CCM, GCM and XTS modes. Furthermore, the proposed design implements in hardware advanced features for AES key secure storage. A flexible interface allows the communication between the hardware accelerator and the chosen processor and makes this implementation suitable to be easily integrated into a generic embedded system. The system has been prototyped and characterized on a Xilinx Zynq 7000 platform. Synthesis results on a 7 nm CMOS Standard-Cell library are proposed too, showing competitive performances and resource usage respect to the State of Art and assessing the portability in different technology libraries of the proposed design. Furthermore, power consumption data are extracted to prove the suitability of the hardware acceleration also in the case of power-constrained devices.

CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes

Nannipieri P.
Co-primo
;
Crocetti L.
Co-primo
;
Di Matteo S.
Co-primo
;
Falaschi F.
Co-primo
;
Fanucci L.
Co-primo
;
Saponara S.
Co-primo
2022

Abstract

This paper presents a System-on-Chip (SoC) implementation of a cryptographic hardware accelerator supporting multiple AES based block cypher modes, including the more advanced CMAC, CCM, GCM and XTS modes. Furthermore, the proposed design implements in hardware advanced features for AES key secure storage. A flexible interface allows the communication between the hardware accelerator and the chosen processor and makes this implementation suitable to be easily integrated into a generic embedded system. The system has been prototyped and characterized on a Xilinx Zynq 7000 platform. Synthesis results on a 7 nm CMOS Standard-Cell library are proposed too, showing competitive performances and resource usage respect to the State of Art and assessing the portability in different technology libraries of the proposed design. Furthermore, power consumption data are extracted to prove the suitability of the hardware acceleration also in the case of power-constrained devices.
978-3-030-95497-0
978-3-030-95498-7
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/1143050
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