CINECA IRIS Institutional Research Information System

DINELLI, GIANMARCO
 Distribuzione geografica
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Continente #
NA - Nord America 484
EU - Europa 422
AS - Asia 86
AF - Africa 32
SA - Sud America 2
Totale 1.026
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Nazione #
US - Stati Uniti d'America 484
SE - Svezia 178
IT - Italia 161
BG - Bulgaria 38
CN - Cina 30
SG - Singapore 30
FR - Francia 20
CI - Costa d'Avorio 17
SN - Senegal 14
DE - Germania 11
VN - Vietnam 9
HK - Hong Kong 7
FI - Finlandia 5
GB - Regno Unito 5
IN - India 3
JP - Giappone 3
TR - Turchia 2
UA - Ucraina 2
BR - Brasile 1
EC - Ecuador 1
EG - Egitto 1
ES - Italia 1
NL - Olanda 1
PK - Pakistan 1
SA - Arabia Saudita 1
Totale 1.026
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Città #
Fairfield 75
Chandler 62
Sofia 38
Woodbridge 38
Cambridge 33
Ashburn 32
Houston 31
Seattle 30
Wilmington 27
New York 24
Florence 20
Abidjan 17
Princeton 16
Lawrence 15
Marseille 15
Beijing 14
Dakar 14
Serra 14
Comiso 10
Frankfurt am Main 10
Rome 9
Medford 8
Montecatini Terme 8
Milan 7
San Diego 7
Hong Kong 6
Ann Arbor 5
Pisa 5
Helsinki 4
Pontedera 4
Dong Ket 3
Gallarate 3
Montevarchi 3
Norwalk 3
Redwood City 3
Arzignano 2
Bari 2
Duncan 2
Falls Church 2
Gentilly 2
London 2
Madison 2
San Giuliano Terme 2
San Vincenzo 2
Santa Maria La Carita 2
Tsukuba 2
Vicopisano 2
Villa Castelli 2
Viterbo 2
Acton 1
Al Hazm 1
Aprilia 1
Aversa 1
Cairo 1
Carmagnola 1
Central District 1
Cogliate 1
Dearborn 1
Des Moines 1
Genoa 1
Grenoble 1
Grosseto 1
Hyderabad 1
Istanbul 1
Kocaeli 1
Lappeenranta 1
Livorno 1
Los Angeles 1
Lucca 1
Napoli 1
Parabiago 1
Pittsburgh 1
Poli 1
Quito 1
Renfrew 1
San Lucido 1
Santa Maria Capua Vetere 1
São Paulo 1
Tappahannock 1
Tianjin 1
Trieste 1
Venice 1
Washington 1
Totale 675
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Nome #
An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick 102
A complete egse solution for the spacewire and spacefibre protocol based on the pxi industry standard 93
Design of a SpaceFibre High-Speed Satellite Interface ASIC 88
A SpaceFibre multi lane codec System on a Chip: Enabling technology for low cost satellite EGSE 85
A configurable hardware word re-ordering block for multi-lane communication protocols: Design and use case 83
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA 78
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus 78
Design of a reduced SpaceFibre interface: An enabling technology for low-cost spacecraft high-speed data-handling 74
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface 63
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator 63
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation 57
MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs 52
SpaceART SpaceWire and SpaceFibre Analyser Real-Time 49
An FPGA-based hardware accelerator for CNNs inference on board satellites: Benchmarking with Myriad 2-based solution for the cloudscout case study 42
A multi-cache system for on-chip memory optimization in fpga-based cnn accelerators 30
SpaceWire/SpaceFibre Analyser Real-Time (SpaceART) system extension to the Wizardlink Protocol 6
Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective 6
Totale 1.049
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Categoria #
all - tutte 3.907
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 3.907
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20199 0 0 0 0 0 0 0 0 0 0 4 5
2019/2020132 3 0 1 1 2 7 26 25 25 17 14 11
2020/2021207 4 13 5 0 2 24 44 8 44 21 10 32
2021/2022239 20 3 22 26 39 42 1 3 10 15 28 30
2022/2023310 51 50 26 7 12 32 5 23 71 5 28 0
2023/2024148 9 9 25 7 13 28 15 6 5 10 21 0
Totale 1.049