DI MATTEO, STEFANO
 Distribuzione geografica
Continente #
EU - Europa 380
NA - Nord America 205
AS - Asia 66
AF - Africa 25
OC - Oceania 3
Totale 679
Nazione #
IT - Italia 221
US - Stati Uniti d'America 202
SE - Svezia 75
SG - Singapore 39
DE - Germania 21
FR - Francia 19
CI - Costa d'Avorio 14
SN - Senegal 11
GB - Regno Unito 10
GR - Grecia 7
UA - Ucraina 7
CN - Cina 6
ES - Italia 5
BG - Bulgaria 4
TR - Turchia 4
AU - Australia 3
CZ - Repubblica Ceca 3
IN - India 3
JP - Giappone 3
PT - Portogallo 3
HK - Hong Kong 2
KZ - Kazakistan 2
MX - Messico 2
VN - Vietnam 2
CA - Canada 1
FI - Finlandia 1
HU - Ungheria 1
IL - Israele 1
IR - Iran 1
KR - Corea 1
LU - Lussemburgo 1
PK - Pakistan 1
RO - Romania 1
RS - Serbia 1
TW - Taiwan 1
Totale 679
Città #
Pisa 76
Chandler 45
Empoli 24
Milan 19
New York 18
Florence 17
Fairfield 15
Abidjan 14
Frankfurt am Main 12
Dakar 11
Grenoble 10
Lawrence 10
Princeton 10
Livorno 9
Serra 8
Rosignano Solvay 7
Wilmington 7
Woodbridge 7
Ogden 6
Rome 6
Medford 5
Athens 4
Capannori 4
Houston 4
Lucca 4
Marseille 4
Palermo 4
San Diego 4
Seattle 4
Sofia 4
Beijing 3
Brno 3
Bruino 3
Eskişehir 3
London 3
Nara 3
Shanghai 3
Astana 2
Bari 2
Cambridge 2
Chicago 2
Council Bluffs 2
Dong Ket 2
Gainesville 2
Garching 2
Genoa 2
Grosseto 2
Hong Kong 2
Pescara 2
Pietrasanta 2
Redwood City 2
Stresa 2
Venice 2
Ann Arbor 1
Ashburn 1
Beograd 1
Berlin 1
Bologna 1
Budapest 1
Buffalo 1
Cedar Knolls 1
Chennai 1
Chiswick 1
Edinburgh 1
Gaeta 1
Helsinki 1
Hyderabad 1
Jacksonville 1
Kilburn 1
Kocaeli 1
La Spezia 1
Luxembourg 1
Marco de Canaveses 1
Massa 1
Montecatini Terme 1
Montpellier 1
Nepean 1
Neubiberg 1
Paris 1
Puteaux 1
Querétaro City 1
Saronno 1
Southwark 1
Taichung 1
Thiruvananthapuram 1
Turin 1
Viareggio 1
Vicopisano 1
Washington 1
Totale 461
Nome #
Crypto accelerators for power-efficient and realtime on-chip implementation of secure algorithms 116
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative 71
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 63
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures 59
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes 53
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms 50
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative 49
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 47
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source 47
Secure elliptic curve crypto-processor for real-time iot applications 45
True random number generator based on Fibonacci-Galois ring oscillators for FPGA 41
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative 26
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case 23
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators 14
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments 8
A PUF-Based Secure Boot for RISC-V Architectures 7
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative 2
Totale 721
Categoria #
all - tutte 2.791
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 2.791


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202041 0 0 0 0 0 10 5 11 6 1 8 0
2020/202130 2 0 0 3 2 3 0 2 2 11 1 4
2021/202293 0 0 2 2 5 9 9 3 5 15 24 19
2022/2023289 55 28 20 16 22 22 5 17 67 1 21 15
2023/2024268 12 16 42 19 26 37 46 45 20 5 0 0
Totale 721