CINECA IRIS Institutional Research Information System

NANNIPIERI, PIETRO
 Distribuzione geografica
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Continente #
NA - Nord America 2.032
EU - Europa 1.689
AS - Asia 787
AF - Africa 97
SA - Sud America 5
OC - Oceania 2
Totale 4.612
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Nazione #
US - Stati Uniti d'America 2.009
IT - Italia 730
SE - Svezia 469
CN - Cina 338
SG - Singapore 267
BG - Bulgaria 100
GB - Regno Unito 86
DE - Germania 79
FR - Francia 70
CI - Costa d'Avorio 62
TR - Turchia 42
FI - Finlandia 40
SN - Senegal 33
RU - Federazione Russa 30
HK - Hong Kong 27
VN - Vietnam 27
UA - Ucraina 26
IN - India 22
CA - Canada 21
JP - Giappone 20
KR - Corea 19
GR - Grecia 13
NL - Olanda 11
ES - Italia 8
PL - Polonia 7
TW - Taiwan 7
CY - Cipro 6
AT - Austria 4
BR - Brasile 4
IR - Iran 4
CZ - Repubblica Ceca 3
IE - Irlanda 3
IL - Israele 3
BE - Belgio 2
KZ - Kazakistan 2
MX - Messico 2
RO - Romania 2
AU - Australia 1
CH - Svizzera 1
EC - Ecuador 1
EE - Estonia 1
EG - Egitto 1
HR - Croazia 1
HU - Ungheria 1
MA - Marocco 1
NZ - Nuova Zelanda 1
PT - Portogallo 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
TJ - Tagikistan 1
UZ - Uzbekistan 1
Totale 4.612
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Città #
Santa Clara 314
Fairfield 180
Woodbridge 154
Chandler 151
Singapore 135
Shanghai 126
Milan 113
Ashburn 110
Sofia 100
Houston 98
Serra 95
Pisa 84
Chicago 78
Florence 78
Cambridge 69
Boardman 68
Wilmington 66
Seattle 63
Abidjan 62
New York 61
Beijing 56
Princeton 49
Ann Arbor 48
Frankfurt am Main 44
Lawrence 40
Dakar 33
Marseille 32
London 31
Helsinki 27
Hong Kong 25
Medford 23
Rome 23
Dearborn 19
Fuzhou 19
Izmir 19
Redwood City 19
Empoli 17
Munich 17
Los Angeles 14
Ogden 14
Ottawa 14
Tamworth 14
Istanbul 13
Comiso 12
Dong Ket 10
Kocaeli 10
San Diego 10
Dallas 9
Des Moines 8
Genoa 7
Mill Valley 7
Norwalk 7
Grenoble 6
Limassol 6
Nanjing 6
Torino 6
Balashikha 5
Guangzhou 5
Hefei 5
Napoli 5
Saint Petersburg 5
Seoul 5
Suizenji 5
Vicopisano 5
Auburn University 4
Boulder 4
Changsha 4
Enterprise 4
Lappeenranta 4
Nanchang 4
North York 4
Paris 4
Quanzhou 4
Shenyang 4
Tokyo 4
Venezia 4
Vienna 4
Wroclaw 4
Wuhan 4
Athens 3
Baltimore 3
Bari 3
Bedford 3
Belfast 3
Brno 3
Buffalo 3
Cambourne 3
Capannori 3
Catania 3
Council Bluffs 3
Gif-sur-yvette 3
Grosseto 3
Hyderabad 3
Kyoto 3
Lancaster 3
Livorno 3
Lucca 3
Montecatini Terme 3
Nuremberg 3
Phoenix 3
Totale 3.082
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Nome #
The U-PHOS experience within the ESA student REXUS/BEXUS programme: A real space hands-on opportunity 273
U-PHOS Project: Development of a Large Diameter Pulsating Heat Pipe Experiment on board REXUS 22 258
U-PHOS EXPERIMENT: THERMAL RESPONSE OF A LARGE DIAMETER PULSATING HEAT PIPE ON BOARD REXUS 22 ROCKET 200
Start-up of a large diameter Pulsating Heat Pipe on ground and on board a sounding rocket 186
U-PHOS Project: Experimental Results of A Large Diameter Pulsating Heat Pipe on Board Rexus 22 175
A PXI based implementation of a TLK2711 equivalent interface 153
Pulsating Heat pipe only for Space (PHOS): Results of the REXUS 18 sounding rocket campaign 140
Application of FBG sensors to temperature measurement on board of the REXUS 22 sounding rocket in the framework of the U-PHOS project 139
Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation 111
Upgraded Pulsating Heat Pipe Only For Space (U-Phos): Results of the 22nd Rexus Sounding Rocket Campaign 107
Large Diameter Pulsating Heat Pipes On Board The Esa Rexus 18 Sounding Rocket 106
Thermal Response of a Pulsating Heat Pipe on Board the Rexus 18 Sounding Rocket: PHOS Experiment Chronicles 106
A complete egse solution for the spacewire and spacefibre protocol based on the pxi industry standard 106
Design of a SpaceFibre High-Speed Satellite Interface ASIC 106
A SpaceFibre multi lane codec System on a Chip: Enabling technology for low cost satellite EGSE 99
A configurable hardware word re-ordering block for multi-lane communication protocols: Design and use case 97
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA 97
PHOS EXPERIMENT: THERMAL RESPONSE OF A LARGE DIAMETER PULSATING HEAT PIPE ON BOARD REXUS 18 ROCKET 93
VHDL design of a spacefibre routing switch 92
Phos Experiment: implementation and test of a Large Diameter Pulsating Heat Pipe On Board Rexus 18 Rocket 90
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus 90
SHINe: Simulator for satellite on-board high-speed networks featuring SpaceFibre and SpaceWire protocols 89
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution 87
Design of a spacewire/spacefibre EGSE system based on PXI industry standard 86
Design of a reduced SpaceFibre interface: An enabling technology for low-cost spacecraft high-speed data-handling 86
An Investigation on SpaceFibre Protocol Maturity: Interoperability Tests 84
Exploiting LabVIEW FPGA Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards 80
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface 79
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 78
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes 74
Phos project: Lesson learned from experimenting a pulsating heat pipe on board a sounding rocket (REXUS18) and refurbishment strategies 72
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation 70
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms 65
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative 62
SpaceART SpaceWire and SpaceFibre Analyser Real-Time 61
Secure elliptic curve crypto-processor for real-time iot applications 60
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source 60
True random number generator based on Fibonacci-Galois ring oscillators for FPGA 54
A representative SpaceFibre network evaluation: Features, performances and future trends 53
A PUF-Based Secure Boot for RISC-V Architectures 48
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative 48
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture 48
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case 38
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators 35
SystemVerilog UVM-based Verification Environment for a SpaceFibre Router 34
ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components 34
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario 33
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators 31
SpaceWire/SpaceFibre Analyser Real-Time (SpaceART) system extension to the Wizardlink Protocol 30
Fault Detection Exploiting Artificial Intelligence in Satellite Systems 28
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip 28
Inference and Evaluation of Deep Convolutional Neural Networks on Microchip's Hardware Accelerator VectorBlox 26
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments 26
Towards the Extension of FPG-AI Toolflow to RNN Deployment on FPGAs for On-board Satellite Applications 23
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry 22
SpaceWire Codec VIP: An innovative architecture of UVM-based Verification Environment: SpaceWire Test and Verification, Short Paper 22
Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective 21
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative 19
SpaceFibre Network Discovery and Configuration Protocol Development 18
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites 18
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications 18
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload 15
Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems 15
Satellite High-Speed On-Board Data Handling: From a Wizardlink Equivalent Transceiver To a Full SpaceFibre Interface 14
Eye Diagram Analyser for Space High-Speed Serial Links: A Tool for Evaluating Signal Integrity in SpaceFibre Links 13
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine 4
SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems 4
Totale 4.837
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Categoria #
all - tutte 16.034
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 16.034
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020364 0 0 0 0 0 0 81 60 73 69 40 41
2020/2021375 9 22 12 6 19 62 64 12 66 43 6 54
2021/2022660 36 11 35 62 119 83 21 14 56 36 68 119
2022/2023884 143 119 62 24 47 73 23 49 222 5 102 15
2023/2024860 53 64 131 51 81 102 61 57 19 51 60 130
2024/2025957 62 90 83 175 253 233 61 0 0 0 0 0
Totale 4.837