CINECA IRIS Institutional Research Information System

NANNIPIERI, PIETRO
 Distribuzione geografica
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Continente #
NA - Nord America 1.676
EU - Europa 1.599
AS - Asia 470
AF - Africa 96
SA - Sud America 5
OC - Oceania 2
Totale 3.848
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Nazione #
US - Stati Uniti d'America 1.654
IT - Italia 698
SE - Svezia 469
SG - Singapore 168
CN - Cina 138
BG - Bulgaria 98
GB - Regno Unito 84
FR - Francia 66
DE - Germania 63
CI - Costa d'Avorio 62
SN - Senegal 33
TR - Turchia 30
VN - Vietnam 27
FI - Finlandia 26
HK - Hong Kong 26
UA - Ucraina 25
IN - India 22
RU - Federazione Russa 21
CA - Canada 20
JP - Giappone 19
KR - Corea 18
GR - Grecia 13
NL - Olanda 9
ES - Italia 7
PL - Polonia 7
TW - Taiwan 7
CY - Cipro 6
BR - Brasile 4
IR - Iran 4
CZ - Repubblica Ceca 3
IL - Israele 3
AT - Austria 2
BE - Belgio 2
MX - Messico 2
RO - Romania 2
AU - Australia 1
CH - Svizzera 1
EC - Ecuador 1
EE - Estonia 1
EG - Egitto 1
HU - Ungheria 1
IE - Irlanda 1
KZ - Kazakistan 1
NZ - Nuova Zelanda 1
TH - Thailandia 1
Totale 3.848
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Città #
Fairfield 180
Woodbridge 154
Chandler 151
Milan 113
Ashburn 106
Houston 98
Sofia 98
Serra 95
Chicago 78
Florence 76
Pisa 75
Cambridge 69
Boardman 68
Wilmington 66
Seattle 63
Abidjan 62
New York 61
Beijing 56
Princeton 49
Ann Arbor 48
Frankfurt am Main 44
Lawrence 40
Singapore 38
Dakar 33
Marseille 32
London 31
Hong Kong 24
Medford 23
Rome 21
Dearborn 19
Izmir 19
Redwood City 19
Empoli 17
Helsinki 14
Ogden 14
Ottawa 14
Tamworth 14
Los Angeles 13
Comiso 12
Dong Ket 10
Kocaeli 10
San Diego 10
Dallas 9
Des Moines 8
Genoa 7
Mill Valley 7
Norwalk 7
Grenoble 6
Limassol 6
Nanjing 6
Torino 6
Balashikha 5
Hefei 5
Napoli 5
Saint Petersburg 5
Seoul 5
Suizenji 5
Vicopisano 5
Auburn University 4
Boulder 4
Enterprise 4
Nanchang 4
North York 4
Shenyang 4
Tokyo 4
Venezia 4
Wroclaw 4
Athens 3
Baltimore 3
Bari 3
Bedford 3
Belfast 3
Brno 3
Buffalo 3
Cambourne 3
Capannori 3
Catania 3
Changsha 3
Gif-sur-yvette 3
Grosseto 3
Guangzhou 3
Hyderabad 3
Kyoto 3
Lancaster 3
Lappeenranta 3
Livorno 3
Montecatini Terme 3
Paris 3
Phoenix 3
Shanghai 3
Sogang 3
Thiruvananthapuram 3
Venice 3
Washington 3
Arzignano 2
Brighton 2
Chennai 2
Council Bluffs 2
Eindhoven 2
Espoo 2
Totale 2.463
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Nome #
The U-PHOS experience within the ESA student REXUS/BEXUS programme: A real space hands-on opportunity 259
U-PHOS Project: Development of a Large Diameter Pulsating Heat Pipe Experiment on board REXUS 22 249
U-PHOS EXPERIMENT: THERMAL RESPONSE OF A LARGE DIAMETER PULSATING HEAT PIPE ON BOARD REXUS 22 ROCKET 186
Start-up of a large diameter Pulsating Heat Pipe on ground and on board a sounding rocket 173
U-PHOS Project: Experimental Results of A Large Diameter Pulsating Heat Pipe on Board Rexus 22 161
A PXI based implementation of a TLK2711 equivalent interface 142
Pulsating Heat pipe only for Space (PHOS): Results of the REXUS 18 sounding rocket campaign 129
Application of FBG sensors to temperature measurement on board of the REXUS 22 sounding rocket in the framework of the U-PHOS project 129
Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation 101
Upgraded Pulsating Heat Pipe Only For Space (U-Phos): Results of the 22nd Rexus Sounding Rocket Campaign 99
Thermal Response of a Pulsating Heat Pipe on Board the Rexus 18 Sounding Rocket: PHOS Experiment Chronicles 96
A complete egse solution for the spacewire and spacefibre protocol based on the pxi industry standard 95
Large Diameter Pulsating Heat Pipes On Board The Esa Rexus 18 Sounding Rocket 92
Design of a SpaceFibre High-Speed Satellite Interface ASIC 90
A SpaceFibre multi lane codec System on a Chip: Enabling technology for low cost satellite EGSE 87
A configurable hardware word re-ordering block for multi-lane communication protocols: Design and use case 85
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA 83
PHOS EXPERIMENT: THERMAL RESPONSE OF A LARGE DIAMETER PULSATING HEAT PIPE ON BOARD REXUS 18 ROCKET 82
VHDL design of a spacefibre routing switch 82
Phos Experiment: implementation and test of a Large Diameter Pulsating Heat Pipe On Board Rexus 18 Rocket 80
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus 80
An Investigation on SpaceFibre Protocol Maturity: Interoperability Tests 76
Design of a spacewire/spacefibre EGSE system based on PXI industry standard 76
Design of a reduced SpaceFibre interface: An enabling technology for low-cost spacecraft high-speed data-handling 75
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution 75
SHINe: Simulator for satellite on-board high-speed networks featuring SpaceFibre and SpaceWire protocols 74
Exploiting LabVIEW FPGA Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards 71
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative 66
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface 65
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation 59
Phos project: Lesson learned from experimenting a pulsating heat pipe on board a sounding rocket (REXUS18) and refurbishment strategies 58
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes 58
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms 54
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative 52
SpaceART SpaceWire and SpaceFibre Analyser Real-Time 51
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source 50
Secure elliptic curve crypto-processor for real-time iot applications 49
A representative SpaceFibre network evaluation: Features, performances and future trends 46
True random number generator based on Fibonacci-Galois ring oscillators for FPGA 43
Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative 38
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture 38
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case 27
ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components 23
A PUF-Based Secure Boot for RISC-V Architectures 21
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators 20
Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators 20
SystemVerilog UVM-based Verification Environment for a SpaceFibre Router 18
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip 16
Fault Detection Exploiting Artificial Intelligence in Satellite Systems 14
SpaceWire/SpaceFibre Analyser Real-Time (SpaceART) system extension to the Wizardlink Protocol 12
Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments 11
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry 10
Towards the Extension of FPG-AI Toolflow to RNN Deployment on FPGAs for On-board Satellite Applications 10
SpaceFibre Network Discovery and Configuration Protocol Development 10
SpaceWire Codec VIP: An innovative architecture of UVM-based Verification Environment: SpaceWire Test and Verification, Short Paper 9
Next-Generation High-Speed Satellite Interconnect: Disclosing the SpaceFibre Protocol – A System Perspective 9
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario 9
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative 7
Satellite High-Speed On-Board Data Handling: From a Wizardlink Equivalent Transceiver To a Full SpaceFibre Interface 7
Inference and Evaluation of Deep Convolutional Neural Networks on Microchip's Hardware Accelerator VectorBlox 6
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications 6
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites 5
Eye Diagram Analyser for Space High-Speed Serial Links: A Tool for Evaluating Signal Integrity in SpaceFibre Links 4
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload 4
Totale 4.032
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Categoria #
all - tutte 13.014
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 13.014
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020488 0 0 34 15 20 55 81 60 73 69 40 41
2020/2021375 9 22 12 6 19 62 64 12 66 43 6 54
2021/2022660 36 11 35 62 119 83 21 14 56 36 68 119
2022/2023884 143 119 62 24 47 73 23 49 222 5 102 15
2023/2024860 53 64 131 51 81 102 61 57 19 51 60 130
2024/2025152 62 90 0 0 0 0 0 0 0 0 0 0
Totale 4.032