CINECA IRIS Institutional Research Information System

TERRENI, PIERANGELO
 Distribuzione geografica
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Continente #
NA - Nord America 6178
EU - Europa 2176
AS - Asia 956
AF - Africa 153
SA - Sud America 4
OC - Oceania 1
Totale 9468
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Nazione #
US - Stati Uniti d'America 5989
CN - Cina 647
SE - Svezia 511
IT - Italia 430
BG - Bulgaria 332
UA - Ucraina 222
DE - Germania 220
CA - Canada 188
TR - Turchia 169
FI - Finlandia 145
FR - Francia 120
VN - Vietnam 112
GB - Regno Unito 107
SN - Senegal 103
CI - Costa d'Avorio 37
BE - Belgio 29
RU - Federazione Russa 25
NG - Nigeria 12
IN - India 10
GR - Grecia 6
CH - Svizzera 5
KR - Corea 5
IE - Irlanda 4
RO - Romania 4
CZ - Repubblica Ceca 3
ES - Italia 3
NL - Olanda 3
BR - Brasile 2
DK - Danimarca 2
HK - Hong Kong 2
HU - Ungheria 2
ID - Indonesia 2
IR - Iran 2
JP - Giappone 2
SG - Singapore 2
AR - Argentina 1
AT - Austria 1
AU - Australia 1
BN - Brunei Darussalam 1
HR - Croazia 1
IL - Israele 1
MU - Mauritius 1
MX - Messico 1
PE - Perù 1
PK - Pakistan 1
PL - Polonia 1
Totale 9468
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Città #
Woodbridge 988
Ann Arbor 885
Houston 696
Fairfield 602
Chandler 549
Sofia 332
Jacksonville 315
Beijing 241
Seattle 214
Ashburn 205
Wilmington 201
Cambridge 193
Ottawa 186
Izmir 168
Princeton 129
Lawrence 128
Nanjing 116
Dakar 103
Marseille 103
Dearborn 100
Medford 80
Des Moines 64
Serra 61
Nanchang 58
Dong Ket 53
Jüchen 49
Boulder 42
Abidjan 37
Düsseldorf 36
San Diego 34
Kunming 32
Brussels 29
Redwood City 27
Shenyang 27
Florence 26
Changsha 25
Tianjin 24
Jiaxing 18
Hebei 16
Boardman 15
Guangzhou 14
Hangzhou 14
Hefei 14
Auburn Hills 13
Los Angeles 13
Philadelphia 13
Frankfurt am Main 12
Lagos 12
Latina 12
Indiana 11
Norwalk 11
Lucca 10
Milan 10
Orange 10
Shanghai 9
Changchun 7
Pisa 7
Rome 7
Verona 7
Alessandria 6
San Francisco 6
Southend 6
London 5
Jinan 4
Lanzhou 4
Ningbo 4
Nürnberg 4
Aosta 3
Bremen 3
New York 3
Prato 3
Rubano 3
Anghiari 2
Budapest 2
Fiumicino 2
Groningen 2
Helsinki 2
Ilanz 2
Madrid 2
Newbury 2
Nichelino 2
Simi Valley 2
Tokyo 2
Torino 2
Wuhan 2
Zurich 2
Altofonte 1
Amsterdam 1
Atlanta 1
Bandar Seri Begawan 1
Baotou 1
Borgo San Lorenzo 1
Capannori 1
Central District 1
Centro 1
Chengdu 1
Chicago 1
Como 1
Copenhagen 1
Costa Mesa 1
Totale 7509
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Nome #
Closed-Loop ELectronic Fuel Injection for Spark-Ignited Engines 134
Automated design of FFT/IFFT processors for advanced telecom applications 128
VLSI systolic filter with ternary coefficients for delta-modulated signals 126
Low-Power VLSI Architectures for 3D Discrete Cosine Transform (DCT) 118
Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications 117
Design of a low-power VLSI macrocell for nonlinear adaptive video noise reduction 117
A Single Chip Adaptive Filter for Delta-Modulated Signals 116
Low power VLSI Architectures for 3D Discrete Cosine Transform (DCT) 116
Topological conditions for the unique solvability of linear time-invariant and time-varying networks 112
CMOS readout chip for pixel detectors 111
Correlation between thermal and generation recombination noise sources: Analytical and Monte Carlo approaches 111
Hardware building blocks of a hierarchical battery management system for a fuel cell HEV 110
Sensor Modeling, Low-Complexity Fusion Algorithms, and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles 110
Dedicated systolic VLSI circuit as adaptive filter for acoustic echo canceller 109
Conditions for the existence and uniqueness of DC solutions of networks containing nonlinear OpAmps with ideal model 107
Switching-based topologies for high-efficiency audio amplifiers 107
Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications 107
A Software Defined Radio Transponder for Low-Orbit Satellite Communications 107
Mitigating Radiation Effects on ICs at Device and Architectural Levels: the SpaceWire Router Case Study 104
Enriching an analog platform for analog-to-digital converter design 103
Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier 103
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures 103
Nonequilibrium velocity autocorrelation function for semiconductors in the presence of trapping phenomena 103
Performance estimation of data-flow applications for IP-based system design 101
BIT-SLICE DIGITAL SIGNAL PROCESSOR FOR HIGH BAUD RATE MODEMS 97
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18 um CMOS with 5.8GHz ERBW 97
Breakdown Ignition System for S.I. Engines: Evolution, Characterisation and Diagnostic 97
Mixed-Signal Architectures for High Efficiency and Low Distortion Digital Audio Processing and Power Amplification 96
Efficient Polynomial Inversion for the Linearization of Pipeline ADCs 94
Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADC 94
Architectural-level Power Optimization of Microcontroller Cores in Embedded Systems 94
Sensor Modeling and Fusion Algorithms for NOx Measures Towards Zero Emissions Vehicles 94
A Framework for Analog Platform Characterization 94
70-MHz 2-μm CMOS Bit-level Systolic Arrat Median Filter 92
A single-chip 1,200 sinusoid real-time generator for additive synthesis of musical signals 92
A VLSI Systolic Filter with ternary coefficients for Delta-Modulated Signals 91
Cost-effective design of AC/DC converter with programmable power amplification 90
Analysis of FPGA Solutions for Baseband Processing in Multi-Carrier Communication Standards for Consumer Applications 90
Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems 90
Hardware accelerator for fast image/video thinning 90
A Novel Bit-Level Systolic Array Median Filter 89
Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems 89
Sensor modeling and data fusion for a safety warning system in hydrogen-based vehicles 89
VLSI macro cell for edge-preserving noise smoothing and deblocking in low-power video communications 88
A DCT systolic chip for digital HDTV 84
Automated Design of FFT/IFFT Processors for Advanced Telecom Applications 84
Radiation tolerant technology implementation of a SpaceWire routing switch 84
A Pyramid Vector Quantizer Chip for HDTV Applications 82
Dedicated Systolic VLSI Circuit as Adaptive Filter for Acoustic Echo Canceller 81
A 500 ps Time-to-Digital Converter (TDC) Integrated Circuit for Nuclear Physics Experiments, as a Result of University-Enterprises cooperation 81
Electronic Systems for High Data-rate and Reliable In-vehicle Communications 81
Mixed-Signal Design Space Exploration for Low-Cost, High-Efficiency Digital Audio Amplifiers 81
A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments 80
Switching based topologies for high-efficiency audio amplifiers 79
Filiera H2 Idrogeno: Risultati e Prospettive 79
Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier 79
Multihit multichannel time-to-digital converter with +/- 1% differential nonlinearity and near optimal time resolution 79
Active balancing in hierarchical Battery Management Systems for large scale Li-ion batteries 78
RADAR ECHO SIMULATOR BASED ON mu P TMS320 77
Realization of an algorithm for image enhancement 77
Digitally Assisted Analog Circuits 77
A new VLSI implementation of Additive Synthesis 77
A digitally controlled shunt capacitor CMOS delay line 77
Self-adaptive algorithmic/architectural design for real-time, low-power video systems 76
Smart Transducer Interface in Embedded Systems for Networked Sensors Based on the Emerging IEEE 1451 Standard: H2 Detection Case Study 76
Linear networks and systems polynomially depending on parameters: Behaviour of the solutions for large and small values 76
LINEAR-NETWORKS AND SYSTEMS DEPENDING POLYNOMIALLY ON PARAMETERS - STABILITY FOR LARGE VALUES SUBJECT TO TOLERANCE ERRORS 76
Design of a Radiation Tolerant Router for On-board Satellite SpaceWire Networking 75
Very long current transients in reverse-biased almost ideal n/sup +/-p junctions 74
Design of ASIP (Application Specific Instruction-set Processor) architectures for image processing in CMOS VLSI technologies 73
Single-chip antenna and LNA architectures for short-range mm-wave transceivers in 65nm CMOS SOI 71
Single-chip antenna and LNA architectures for short-range mm-wave transceivers in 65nm CMOS SOI 70
Context-aware Algorithmic/Architectural Solutions for Real-time Embedded Video Systems 70
VPP Education in Universities: the Pisa experience 70
Architetture dei Sistemi Integrati 69
New Ignition Systems for High-Performance S.I. Engines 68
A QoS Internet Protocol Scheduler on the IXP1200 Network Platform 67
VLSI Design of a Routing Switch for the SpaceWire Serial Link Standard 67
Single-Chip Systolic FIR Filter for Acoustic Echo Cancellation 66
H2 e batterie al litio: un'accoppiata vincente 66
Fondamenti di elettronica 66
Embedded system for brushless motor control in space application 65
Electronic Circuits and Systems for Sustainability and Safety Improvement of Road Transport 64
Intellectual Property Macrocell for SpaceWire Interface Compliant with AMBA-APB Bus 63
An application of a systolic macrocell based VLSI design style: a single-chip high-performance FIR filter 61
Full-Custom Design of Integrated Circuits as Dissertation Exercise for EE Students at the University of Pisa 61
Hierarchical Platform for Battery Management System with Active Balancing 61
1/F-GAMMA NOISE IN THICK-FILM RESISTORS AS AN EFFECT OF TUNNEL AND THERMALLY ACTIVATED EMISSIONS, FROM MEASURES VERSUS FREQUENCY AND TEMPERATURE 61
Italian National Research Council Network for VLSI Circuit Remote Design 61
EQUIVALENT-CIRCUIT AND STATISTICS OF BURST NOISE IN BIPOLAR-TRANSISTORS 60
Single-chip 1,200 sinusoid real-time generator for additive synthesis of music signals 59
VLSI Design of a Scheduler to Support Quality of Service in IP Networks 59
Active balancing in hierarchical Battery Management Systems for large scale Li-ion batteries 59
Optimization of ADC Power Consumption 58
Adaptive Algorithm for Fast Motion Estimation in H.264/MPEG-4 AVC 57
Application of a Systolic Macrocell-Based VLSI Design Style to the Design of a Single-Chip High-Performance FIR Filter 57
Low-power VLSI Architecture for Adaptive Video Noise Reduction 57
A Digitally Controlled Shunt Capacitor CMOS Delay Line 56
MHITIC: 8-channels, 1-ns, multi-hit time-to-digital converter CMOS integrated circuit 53
Architetture VLSI a basso consumo di potenza per il filtraggio adattativo del rumore in sequenze video 53
Totale 8445
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Categoria #
all - tutte 15890
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 15890
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2017/20183 0000 00 00 0003
2018/20191344 73103 19613 4208 10272229173
2019/20201903 26817693128 188219 219136 17512114733
2020/2021890 85357952 11237 74114 486048146
2021/20221216 221162171 231212 2956 452271320
2022/20231590 17014087128 188229 18125 4116880
Totale 9564