ROSSI, DANIELE
 Distribuzione geografica
Continente #
NA - Nord America 2.748
EU - Europa 1.349
AS - Asia 445
AF - Africa 21
SA - Sud America 2
Continente sconosciuto - Info sul continente non disponibili 1
Totale 4.566
Nazione #
US - Stati Uniti d'America 2.742
IT - Italia 922
SG - Singapore 212
BG - Bulgaria 183
SE - Svezia 119
VN - Vietnam 100
CN - Cina 57
HK - Hong Kong 24
TR - Turchia 22
GB - Regno Unito 20
SN - Senegal 20
RU - Federazione Russa 19
FR - Francia 16
GR - Grecia 15
DE - Germania 13
IN - India 12
NL - Olanda 10
FI - Finlandia 8
AT - Austria 6
CH - Svizzera 6
ID - Indonesia 4
CA - Canada 3
JP - Giappone 3
KR - Corea 3
MX - Messico 3
PH - Filippine 3
PT - Portogallo 3
ES - Italia 2
IL - Israele 2
RO - Romania 2
TW - Taiwan 2
AL - Albania 1
BR - Brasile 1
CI - Costa d'Avorio 1
CZ - Repubblica Ceca 1
EC - Ecuador 1
EU - Europa 1
IE - Irlanda 1
LU - Lussemburgo 1
MD - Moldavia 1
MY - Malesia 1
Totale 4.566
Città #
Milan 574
Santa Clara 516
Fairfield 372
Woodbridge 192
Sofia 183
Wilmington 165
Seattle 163
Ashburn 160
Princeton 152
Houston 132
Cambridge 118
Boardman 110
New York 105
Singapore 88
Lawrence 80
Medford 76
Ann Arbor 42
Dong Ket 41
Pisa 39
San Diego 39
Rome 35
Pietrasanta 28
Hong Kong 24
Chandler 23
Dakar 20
Ogden 19
Norwalk 17
San Vincenzo 15
Istanbul 13
Shenzhen 11
Nanjing 9
Amsterdam 7
Kolkata 7
London 7
Lucca 7
Pescara 7
Shanghai 7
Livorno 6
Orenburg 6
Redwood City 6
Athens 5
Baotou 5
Grenoble 5
Quanzhou 5
Vienna 5
Washington 5
Florence 4
Lappeenranta 4
Serra 4
Bruino 3
Cebu City 3
Dallas 3
Eskişehir 3
Frankfurt (Oder) 3
Lonato 3
Massa 3
Mexico City 3
Nanchang 3
Palermo 3
Bern 2
Boulder 2
Delhi 2
Fuzhou 2
Gainesville 2
Garching 2
Guangzhou 2
Jersey City 2
Jerusalem 2
Los Angeles 2
Mountain View 2
New Bedfont 2
Redmond 2
Surabaya 2
Taipei 2
Tokyo 2
Toronto 2
Yuseong-gu 2
Abidjan 1
Acton 1
Altopascio 1
Brno 1
Chisinau 1
Dublin 1
Enfield 1
Esslingen am Neckar 1
Evercreech 1
Geneva 1
Hangzhou 1
Hanoi 1
Hebei 1
Helsinki 1
Islington 1
Jakarta 1
Kent 1
Kuala Lumpur 1
Linyi 1
Luxembourg 1
Marco de Canaveses 1
Mitcham 1
Modena 1
Totale 3.752
Nome #
Modeling and detection of hotspot in shaded photovoltaic cells 109
Collective-Aware System-on-Chips for Dependable IoT Applications 87
BTI aware thermal management for reliable DVFS designs 86
Aging Benefits in Nanometer CMOS Designs 85
Low power probabilistic online monitoring of systematic erroneous behaviour 83
Analysis of BTI aging of level shifters 80
Model for thermal behavior of shaded photovoltaic cells under hot-spot condition 78
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories 77
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures 76
Reliable Power Gating with NBTI Aging Benefits 76
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 76
Low cost error monitoring for improved maintainability of IoT applications 75
Impact of Bias Temperature Instability on Soft Error Susceptibility 72
Clock faults induced min and max delay violations 71
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection 69
Self-checking monitor for NBTI due degradation 68
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure 67
Path (min) delay faults and their impact on self-checking circuits' operation 65
Leveraging CMOS Aging for Efficient Microelectronics Design 65
Analysis of the impact of bus implemented EDCs on on-chip SSN 64
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits 63
Checkers' no-harm alarms and design approaches to tolerate Them 63
The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology 62
Risks for signal integrity in system in package and possible remedies 62
Accurate linear model for SET critical charge estimation 62
Diagnosis of power switches with power-distribution-network consideration 61
Power droop reduction during Launch-On-Shift scan-based logic BIST 60
Modeling crosstalk effects in CNT bus architectures 60
null 60
Hardware Trojan Detection on a PCB Through Differential Power Monitoring 60
Multiple transient faults in logic: An issue for next generation ICs? 59
Latch susceptibility to transient faults and new hardening approach 59
Scalable Approach for Power Droop Reduction during Scan-Based Logic BIST 58
Low cost concurrent error detection strategy for the control logic of high performance microprocessors and its application to the instruction decoder 58
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories 58
DFT Architecture with Power-Distribution-Network Consideration for Delay-Based Power Gating Test 57
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects 57
Leakage current analysis for diagnosis of bridge defects in power-gating designs 56
A novel dual-walled CNT bus architecture with reduced cross-coupling features 56
The effects of ageing on the reliability and performance of integrated circuits 56
Low-cost on-chip clock jitter measurement scheme 55
Run-time Detection and Mitigation of Power-Noise Viruses 55
Recycled IC detection through aging sensor 55
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors 55
On transistor level gate sizing for increased robustness to transient faults 55
Fast and low-cost clock deskew buffer 54
High-performance robust latches 54
Impact of Aging Phenomena on Latches' Robustness 54
Novel low-cost aging sensor 52
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance 49
Impact of aging phenomena on soft error susceptibility 49
Error correcting code analysis for cache memory high reliability and performance 47
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies 46
Exploiting ECC redundancy to minimize crosstalk impact 45
Faults affecting energy-harvesting circuits of self-powered wireless sensors and their possible concurrent detection 45
New ECC for crosstalk impact minimization 43
Power consumption of fault tolerant busses 43
Coding techniques for low switching noise in fault tolerant busses 42
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating 42
null 41
Novel approach to reduce power droop during scan-based logic BIST 41
Transient fault and soft error on-die monitoring scheme 41
Design of Linear and Planar Arrays with Low Sidelobe Levels and High Directivity Using Two-way Array Factor 40
Low cost nbti degradation detection and masking approaches 40
Low cost and high speed embedded two-rail code checker 39
Model for transient fault susceptibility of combinational circuits 39
Simultaneous switching noise: The relation between bus layout and coding 38
Won't on-chip clock calibration guarantee performance boost and product quality? 37
Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic 37
Error correcting strategy for high speed and high density reliable flash memories 37
HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement 36
The other side of the timing equation: A result of clock faults 36
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology 35
Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology 33
Self-checking voter for high speed TMR systems 31
Configurable error control scheme for NoC signal integrity 31
Secure communication protocol for wireless sensor networks 31
Novel high speed robust latch 30
Online Remaining Useful Lifetime prediction using support vector regression 30
Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs 30
Polynomial based key distribution scheme for WPAN 29
Novel Approach to Enhance Spectral Width of the Interrogating Signal for Reading Ultrawideband Chipless RFID Tags 28
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs 27
null 26
A New Error Correcting Coding Technique to Tolerate Soft Errors 26
A Support Vector Regression based Machine Learning method for on-chip Aging Estimation 26
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications 23
An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments 22
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS technology 22
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current 22
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments 21
Embedded Platforms for Trusted Edge Computing towards Quality Assurance along the Supply Chain 19
null 17
Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems 14
Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications 13
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas 12
RTL Flow for the Power Side-Channel Resilience Assessment of a Post-quantum SHA-3 Accelerator 11
Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function 11
Design and Experimental Verification of a 6.25 GHz PLL for Harsh Temperature Conditions in 65 nm CMOS Technology 11
Can clock faults be detected through functional test? 11
Totale 4.800
Categoria #
all - tutte 19.989
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 19.989


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020360 0 0 0 0 0 0 65 95 101 49 16 34
2020/20211.227 75 40 40 26 14 89 122 50 144 68 454 105
2021/2022752 7 14 11 11 107 152 12 31 60 18 92 237
2022/2023387 155 4 13 33 7 45 6 22 54 26 20 2
2023/20241.332 136 166 166 176 217 166 116 21 35 2 46 85
2024/2025821 7 110 36 99 330 239 0 0 0 0 0 0
Totale 4.879