ROSSI, DANIELE
 Distribuzione geografica
Continente #
NA - Nord America 2.104
EU - Europa 1.294
AS - Asia 357
AF - Africa 21
SA - Sud America 2
Continente sconosciuto - Info sul continente non disponibili 1
Totale 3.779
Nazione #
US - Stati Uniti d'America 2.100
IT - Italia 896
BG - Bulgaria 183
SG - Singapore 171
SE - Svezia 119
VN - Vietnam 100
CN - Cina 35
HK - Hong Kong 22
SN - Senegal 20
GB - Regno Unito 17
GR - Grecia 15
FR - Francia 14
RU - Federazione Russa 12
DE - Germania 10
IN - India 9
TR - Turchia 9
FI - Finlandia 6
NL - Olanda 5
AT - Austria 4
CH - Svizzera 3
KR - Corea 3
MX - Messico 3
PT - Portogallo 3
ES - Italia 2
ID - Indonesia 2
IL - Israele 2
RO - Romania 2
TW - Taiwan 2
BR - Brasile 1
CA - Canada 1
CI - Costa d'Avorio 1
CZ - Repubblica Ceca 1
EC - Ecuador 1
EU - Europa 1
JP - Giappone 1
LU - Lussemburgo 1
MD - Moldavia 1
MY - Malesia 1
Totale 3.779
Città #
Milan 574
Fairfield 372
Woodbridge 192
Sofia 183
Wilmington 165
Seattle 163
Ashburn 157
Princeton 152
Houston 132
Cambridge 118
New York 105
Lawrence 80
Medford 76
Singapore 51
Ann Arbor 42
Dong Ket 41
San Diego 39
Rome 35
Pietrasanta 28
Pisa 24
Chandler 23
Hong Kong 22
Dakar 20
Ogden 19
Norwalk 17
San Vincenzo 15
Shenzhen 11
Nanjing 9
Lucca 7
Pescara 7
Livorno 6
Orenburg 6
Redwood City 6
Amsterdam 5
Athens 5
Baotou 5
Grenoble 5
Kolkata 5
London 5
Washington 5
Florence 4
Serra 4
Vienna 4
Bruino 3
Eskişehir 3
Frankfurt (Oder) 3
Lappeenranta 3
Massa 3
Mexico City 3
Nanchang 3
Palermo 3
Shanghai 3
Bern 2
Boulder 2
Dallas 2
Delhi 2
Gainesville 2
Garching 2
Guangzhou 2
Jersey City 2
Jerusalem 2
Mountain View 2
New Bedfont 2
Redmond 2
Taipei 2
Yuseong-gu 2
Abidjan 1
Acton 1
Altopascio 1
Brno 1
Chisinau 1
Enfield 1
Esslingen am Neckar 1
Evercreech 1
Geneva 1
Hanoi 1
Hebei 1
Islington 1
Jakarta 1
Kent 1
Kuala Lumpur 1
Luxembourg 1
Marco de Canaveses 1
Mitcham 1
Modena 1
Monte San Pietro 1
Montpellier 1
Napoli 1
Neubiberg 1
New Delhi 1
Paris 1
Ponsacco 1
Pune 1
Quito 1
Shenyang 1
Tappahannock 1
Toronto 1
Valdagno 1
Vicopisano 1
Wirral 1
Totale 3.033
Nome #
Modeling and detection of hotspot in shaded photovoltaic cells 102
Collective-Aware System-on-Chips for Dependable IoT Applications 81
BTI aware thermal management for reliable DVFS designs 80
Aging Benefits in Nanometer CMOS Designs 79
Low power probabilistic online monitoring of systematic erroneous behaviour 77
Analysis of BTI aging of level shifters 74
Model for thermal behavior of shaded photovoltaic cells under hot-spot condition 72
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories 71
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 70
Reliable Power Gating with NBTI Aging Benefits 69
Low cost error monitoring for improved maintainability of IoT applications 69
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures 65
Impact of Bias Temperature Instability on Soft Error Susceptibility 65
Clock faults induced min and max delay violations 65
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection 63
Self-checking monitor for NBTI due degradation 62
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure 61
Path (min) delay faults and their impact on self-checking circuits' operation 59
Analysis of the impact of bus implemented EDCs on on-chip SSN 58
Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit 58
Checkers' no-harm alarms and design approaches to tolerate Them 57
Leveraging CMOS Aging for Efficient Microelectronics Design 57
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits 56
Risks for signal integrity in system in package and possible remedies 56
Accurate linear model for SET critical charge estimation 56
The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology 55
Diagnosis of power switches with power-distribution-network consideration 55
Power droop reduction during Launch-On-Shift scan-based logic BIST 54
Modeling crosstalk effects in CNT bus architectures 54
Multiple transient faults in logic: An issue for next generation ICs? 53
Latch susceptibility to transient faults and new hardening approach 53
Low cost concurrent error detection strategy for the control logic of high performance microprocessors and its application to the instruction decoder 52
Scalable Approach for Power Droop Reduction during Scan-Based Logic BIST 51
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects 51
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories 51
Hardware Trojan Detection on a PCB Through Differential Power Monitoring 51
DFT Architecture with Power-Distribution-Network Consideration for Delay-Based Power Gating Test 50
A novel dual-walled CNT bus architecture with reduced cross-coupling features 50
The effects of ageing on the reliability and performance of integrated circuits 50
Leakage current analysis for diagnosis of bridge defects in power-gating designs 49
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors 49
On transistor level gate sizing for increased robustness to transient faults 49
Low-cost on-chip clock jitter measurement scheme 48
Run-time Detection and Mitigation of Power-Noise Viruses 48
Recycled IC detection through aging sensor 48
Fast and low-cost clock deskew buffer 48
High-performance robust latches 48
Impact of Aging Phenomena on Latches' Robustness 47
Novel low-cost aging sensor 44
Impact of aging phenomena on soft error susceptibility 43
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance 42
Error correcting code analysis for cache memory high reliability and performance 41
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies 40
Exploiting ECC redundancy to minimize crosstalk impact 39
Faults affecting energy-harvesting circuits of self-powered wireless sensors and their possible concurrent detection 39
Run-Time Protection of Multi-Core Processors from Power-Noise Denial-of-Service Attacks 39
New ECC for crosstalk impact minimization 37
Power consumption of fault tolerant busses 37
Coding techniques for low switching noise in fault tolerant busses 36
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating 36
Transient fault and soft error on-die monitoring scheme 35
Low cost nbti degradation detection and masking approaches 34
Novel approach to reduce power droop during scan-based logic BIST 34
Low cost and high speed embedded two-rail code checker 33
Model for transient fault susceptibility of combinational circuits 33
Simultaneous switching noise: The relation between bus layout and coding 32
Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic 31
Won't on-chip clock calibration guarantee performance boost and product quality? 30
The other side of the timing equation: A result of clock faults 30
Error correcting strategy for high speed and high density reliable flash memories 30
Self-checking voter for high speed TMR systems 25
Configurable error control scheme for NoC signal integrity 25
Secure communication protocol for wireless sensor networks 25
Novel high speed robust latch 24
Design of Linear and Planar Arrays with Low Sidelobe Levels and High Directivity Using Two-way Array Factor 23
Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology 22
Polynomial based key distribution scheme for WPAN 22
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology 21
Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs 21
Online Remaining Useful Lifetime prediction using support vector regression 20
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs 19
A New Error Correcting Coding Technique to Tolerate Soft Errors 16
A Support Vector Regression based Machine Learning method for on-chip Aging Estimation 16
Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications 14
Novel Approach to Enhance Spectral Width of the Interrogating Signal for Reading Ultrawideband Chipless RFID Tags 14
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current 14
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications 13
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS technology 11
Embedded Platforms for Trusted Edge Computing towards Quality Assurance along the Supply Chain 10
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas 8
An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments 6
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments 6
HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement 6
Can clock faults be detected through functional test? 5
Checker no-harm alarm robustness 5
Clock calibration faults and their impact on quality of high performance microprocessors 5
High speed and highly testable parallel two-rail code checker 4
Coding scheme for low energy consumption fault-tolerant bus 4
Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function 3
A model for transient fault propagation in combinatorial logic 3
Totale 4.051
Categoria #
all - tutte 16.523
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 16.523


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020360 0 0 0 0 0 0 65 95 101 49 16 34
2020/20211.227 75 40 40 26 14 89 122 50 144 68 454 105
2021/2022752 7 14 11 11 107 152 12 31 60 18 92 237
2022/2023387 155 4 13 33 7 45 6 22 54 26 20 2
2023/20241.332 136 166 166 176 217 166 116 21 35 2 46 85
2024/20257 7 0 0 0 0 0 0 0 0 0 0 0
Totale 4.065